1. Field of the Invention
This invention relates to interconnection circuitry and, more particularly, to apparatus for handling data within a computer system in a manner that a plurality of data sources can transfer information to a plurality of destinations concurrently.
2. History of the Prior Art
The typical computer system utilizes a busing arrangement as its primary interconnection to transfer information from one component of the system to another. In such a system, a component such as a central processor directs information to another component such as main memory by placing the address to which the information is directed on the system address bus and the information on the system data bus. The destination for the information recognizes an address on the address bus within its range of addresses and accepts the information available on the data bus. Each of these buses is made up of a number of conductors (for example, thirty-two) which physically connect to each of the system components. During the time that any particular source of information is utilizing the buses, they are unavailable for use by any other source since all of the conductors of each bus available to carry either address or data information are occupied. Consequently, information may be sent by only one source at a time (although more than one destination may receive information if more than one destination can respond to the same address) since there is no room for information from more than one source at a time on the data or address buses.
In the past, a bus arrangement has sufficed for transferring information in the typical personal computer or work station. However, the requirements for pathways to handle more and more information faster have increased to the point that various functions cannot be performed by the typical busing arrangement. Functions such as the presentation of animated graphics and television require the transfer of so much information that they tend to require that the entire system be devoted to their use. When it is desired to incorporate a number of these functions into the same computer system and to run more than one of them at a time, a busing arrangement is incapable of handling the load.
In order to overcome the limitations of a bus system, it seems apparent that more than one interconnection between system components is necessary. The ultimate arrangement would be one in which each component were connected to each other component. This, however, appears to require a great deal of control circuitry and a very large number of conductors which would probably be used substantially less than full time. As a compromise between the single system bus and the direct connection of all components, various ring arrangements have been suggested. In such an arrangement, each component is directly connected by one-way connection paths to receive information from one single other system component and to send information to another single system component. Thus, all components which would normally be connected to a bus are connected to only two other components in a unidirectional ring. Each component then forwards information around the ring until the information arrives at its destination. Separating the interconnection into individual paths between components isolates the components from all but two other components but increases the amount of traffic which can be handled by the ring interconnect over the amount which may be placed on a system bus because a number of sources of information can communicate with a number of destinations at the same time. This occurs because the isolation allows one system component to send information to a second component while a third component sends information to a fourth component.
In ring-type systems suggested to date, one system component places a packet of information on the ring addressed to another component. The packet is forwarded to the addressed component; and, if that component cannot handle the incoming information, it places a retry command on the ring. The retry command causes the operation to be terminated, the transmitted information to be dumped, and the packet to be re-sent after some delay. The retry operation inherently slows the system when the amount of traffic on the system approaches saturation. In fact, as the amount of information placed on the ring increases in retry systems, the ability to handle that information decreases because the system thrashes as the number of retries increases. In fact, such retry systems typically are able to handle no more than one-third to one-half of theoretically attainable loads.
In order to overcome the problems of proposed ring systems and provide a system capable of transferring much more data than conventional computer arrangements, a new interconnect has been devised which is the subject of U.S. Pat. No. 5,165,019, entitled RING INTERCONNECT SYSTEM ARCHITECTURE, P. Sweazey, filed May 29, 1990, and assigned to the assignee of this invention. This interconnect is made up of a plurality of nodes each such node being associated with at least one of a plurality of computer system components. The nodes are, as in prior art systems, connected in a unidirectional ring in which transmission paths connect each of the nodes to one node which is a source of information and to another node which is a recipient of information.
Each of such nodes includes apparatus for receiving information from and transferring information to the associated one of the system components. When the associated system component desires to transfer information to another system component, it causes the associated node to generate and place a voucher signal on the transmission path to indicate that the node has information to be transmitted to another system component. Each node includes storage space for information and apparatus which responds to the receipt of a voucher signal directed to it as a target node for determining whether the node is able to store information in its storage space. Each node also includes apparatus which responds to a determination that storage space is available by placing a ticket signal to so indicate on the transmission path directed to the node which is to be the source of the information. When a source node receives such a ticket signal, it causes the information packet to be launched on the transmission path. In this manner, no information is propagated on the transmission path until space is available for it at the target node and delays due to information rejection at the target node are eliminated.
Each node also includes circuitry to relay voucher and ticket signals and information which are directed to another node so that information is passed along the transmission path. Moreover, each node includes apparatus for assuring that both voucher and ticket signals are transferred by the node in preference to any information. By this means the transferred information on the transmission path does not get in the way of and delay the signals which control the transmission of that information.
Although such an interconnect system provides substantial benefits over the typical bus interconnection of the prior art, it would be advantageous were the system able to select among the different information to be transferred by the various nodes and transmit first that information which is most urgent. In this manner, the system would be able to resolve conflicts between different types of information and handle information such as sound and video prior to information which does not have the same real time requirements.